Plug fabricating method for dielectric layer

ABSTRACT

A method of fabricating a plug for a hole in a dielectric layer is disclosed. The method includes a first deposition process to partially filling the hole with a conductive material. Later, an etching process is performed at the partially filled hole. In addition, a second deposition process is performed to partially fill the hole with the conductive material again. Finally, the above steps are repeated until the hole is completely filled. The first deposition process and the second deposition process are done using a CVD or a PVD process. In addition, the etching process is done using halogen-containing gas.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method of fabricating a plug in adielectric layer. More particularly, the present invention relates to amethod of fabricating a plug in a dielectric layer having improved gapfill properties.

2. Description of Related Art

As the semiconductor device size continues to shrink geometrically, thecontact hole is becoming smaller and smaller. The atomic layerdeposition (ALD) and pulsed nucleation layer (PNL) deposition methodsare used as the current approaches for improving the gap fill usingtungsten.

Because the shrinking device size is creating a tendency to result inthe greater shrinkage in the horizontal dimension than in the verticaldimension, the increased aspect ratios (height to width) of the devicesare making it increasingly important to develop processes that enableconductive material to fill increasing aspect ratio trenches and viaholes. In high aspect ratio contact structures, the bulk deposition isalso faced with the gap fill problem and the tungsten seams becomes moreserious.

Continuous and complete sidewalls, bottom coverage of the seed layerinside very narrow gaps, pinches-off or seals of the small openings whenused at thicknesses required on the field for a low-resistanceelectrical path are all provided by the ALD. As a result, the layersmade by ALD are too thin on the field and too thick inside the verynarrow gaps. A better method for fabricating a plug in a dielectrichaving improved gap fill properties is required for the aforementionedsmaller contact hole and gaps.

SUMMARY OF THE INVENTION

An objective for the present invention is for providing a method offabricating a plug in a dielectric layer having improved gap fillproperties and reduced key hole.

Based on the above objective, the present invention proposes a method offabricating a plug in a dielectric layer having a hole formed thereinwhich has four main steps, namely a first deposition step, an etchingstep, a second deposition step, and the repeating of the aforementionedconsecutive steps, if necessary, until the hole is filled.

The aforementioned method includes a first deposition process forpartially filling the hole with a conductive material, a first etchingprocess for removing the overhang and pinch-off portions, a seconddeposition process for partially filling the hole with a conductivematerial, and a repeat of all of the aforementioned steps consecutivelyuntil the hole is completely filled with the conductive material.

The first deposition process includes a CVD, a PVD, and a high densityplasma deposition process. It is performed until an overhang is formedon the top of the hole. The conductive material for the first depositionprocess includes tungsten, copper, or aluminum.

The first etching process is a dry etching process or a wet etchingprocess. The dry etching process using a halogen-containing gas as asource gas. The halogen-containing gas is, for example, afluorine-containing gas or a NF₃. The wet etching process is performed,for example, using hydrogen peroxide.

The second deposition process includes a CVD process, a PVD process, anda high density plasma deposition process. It is also performed until anoverhang is formed on the top of the hole. The conductive material forthe second deposition process includes tungsten, copper, or aluminum.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1C are cross-sectional views, schematically illustratinga method for fabricating a plug according to a first embodiment of thepresent invention.

FIG. 2A to FIG. 2C are cross-sectional views, schematically illustratinga method for fabricating a plug according to a second embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1A to FIG. 1C schematically illustrate amulti-deposition-and-etching-step method for fabricating a plugaccording to a first embodiment of the present invention. The method offabricating the plug in a dielectric layer 20 for filling a hole 30 forthe first embodiment of the present invention comprises the steps as thefollowing.

-   a. a first deposition process (step 100) is performed to partially    fill the hole 30 with a conductive material 40;-   b. a first etching process (step 200) is performed;-   c. a second deposition process (step 300) is performed to partially    fill the hole 30 with a conductive material 40; and-   d. repeating step a, b, and c above until the hole 30 is filled with    the conductive material 40.

Referring to FIG. 1A, in this embodiment, the hole 30 exposes the device11, such as conductive region, wire or via, formed in the process layer10 under the dielectric layer 20. However, the hole 30 in presentinvention is not limited by the configuration shown in FIG. 1A and canbe any other structure, such as trench, without exposing the deviceformed in the underlayer. Moreover, the first deposition process (step100) can be a CVD, a PVD, or a high density plasma process. The firstdeposition process (step 100) is performed until an overhang 50 isformed on the top of the hole 30. The conductive material 40 used in thefirst deposition process (step 100) includes tungsten, copper, oraluminum.

As shown in FIG. 1B, the first etching process (step 200) can be a dryetching process or a wet etching process. In the dry etching process(step 210), the first etching process (step 200) is performed using ahalogen-containing gas as a source gas. The halogen-containing gasincludes, for example, a fluorine-containing gas. Preferably, thefluorine-containing gas is a NF₃ gas. While the first etching process(step 200) is the wet etching process, the first etching process (step200) is performed using a wet etching agent such as hydrogen peroxide.

Referring to FIG. 1C, the second deposition process (step 300) can be aCVD, a PVD, or a high density plasma process. The second depositionprocess (step 300) is performed until an overhang 50 is formed on thetop of the hole 30.

FIG. 2A to FIG. 2C schematically illustrate another 3-step method forfabricating a plug according to a second embodiment of the presentinvention. The method of fabricating the plug in a dielectric layer 120for filling a hole 130 corresponding in the second embodiment of thepresent invention comprises the steps as followings:

-   a. a first deposition process (step 400) is performed to partially    fill the hole with a conductive material 150;-   b. an etching process (step 500) is performed; and-   c. a second deposition process (step 600) is performed to fill out    the hole with a conductive material 150.

Referring to FIG. 2A, in this embodiment, the hole 130 exposes thedevice 111, such as conductive region, wire or via, formed in theprocess layer 110 under the dielectric layer 120. However, the hole 130in present invention is not limited by the configuration shown in FIG.2A and can be any other structure, such as trench, without exposing thedevice formed in the underlayer. Furthermore, the first depositionprocess (step 400) can be a CVD, a PVD, or a high density plasmaprocess. The first deposition process (step 400) is performed to form aconductive layer 140 partially filling the hole 130. The conductivematerial 150 used for forming the conductive layer 140 in the firstdeposition process (step 400) includes tungsten, copper, or aluminum.

Referring to FIG. 2B, the etching process (step 500) can be a dryetching process or a wet etching process. While the etching process isthe dry etching process, the etching process is performed using ahalogen-containing gas as a source gas. The halogen-containing gasincludes, for example, a fluorine-containing gas. Preferably, thefluorine-containing gas can be, for example but not limited to, a NF₃gas. While the etching process is the wet etching process, the etchingprocess is performed using a wet etching agent 190 such as hydrogenperoxide.

Referring to FIG. 2C, the second deposition process (step 600) can be aCVD, a PVD, or a high density plasma process. The second depositionprocess (step 600) is performed until the hole 130 is filled.

The present invention provides a multi-deposition-and-etching-stepmethod of fabricating a plug in a dielectric layer. By using the methodof the present invention, since the overhangs of the conductive layer atthe top of the hole formed in the previous deposition process is removedby the successively performed etching process, issue of gap void in thenarrow hole during the gap filling can be successfully overcome. Hence,the no keyhole or seam happens during gap filling an opening with ahigher aspect ratio.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing descriptions, it is intended that the presentinvention covers modifications and variations of this invention if theyfall within the scope of the following claims and their equivalents.

1. A method of fabricating a plug in a dielectric layer, wherein thedielectric layer has a hole, the method comprising: a. performing afirst deposition process to partially fill the hole with a conductivematerial; b. performing a first etching process; c. performing a seconddeposition process to partially fill the hole with the conductivematerial; and d. repeating step a, b, and c until the hole is filledwith the conductive material.
 2. The method of claim 1, wherein thefirst deposition process is performed until an overhang is formed on thetop of the hole.
 3. The method of claim 1, wherein the first depositionprocess includes a CVD process, a PVD process, and a high density plasmadeposition process.
 4. The method of claim 1, wherein, the first etchingprocess includes a dry etching process.
 5. The method of claim 4,wherein, the first etching process is performed using ahalogen-containing gas as a source gas.
 6. The method of claim 1,wherein the second deposition process is performed until an overhang isformed on the top of the hole.
 7. The method of claim 1, wherein thesecond deposition process includes a CVD process, a PVD process, and ahigh density plasma deposition process.
 8. The method of claim 5,wherein the halogen-containing gas comprises a fluorine-containing gas.9. The method of claim 5, wherein the halogen-containing gas is NF3. 10.The method of claim 1, wherein the first etching process comprises a wetetching process.
 11. The method of claim 10, wherein the first etchingprocess is performed by using hydrogen peroxide.
 12. The method of claim1, wherein the conductive material includes tungsten, copper, oraluminum.
 13. A method of fabricating a plug in a dielectric layer,wherein the dielectric layer has a hole, comprising: performing a firstdeposition process to partially fill the hole with a conductivematerial; performing an etching process; and performing a seconddeposition process to fill out the hole with conductive material. 14.The method of claim 13, wherein the first deposition process isperformed until an overhang is formed on the top of the hole.
 15. Themethod of claim 13, wherein the first deposition process includes a CVDprocess, a PVD process, and a high density plasma deposition process.16. The method of claim 13, wherein, the etching process includes a dryetching process.
 17. The method of claim 16, wherein, the etchingprocess is performed using a halogen-containing gas as a source gas. 18.The method of claim 13, wherein the second deposition process includes aCVD process, a PVD process, and a high density plasma depositionprocess.
 19. The method of claim 17, wherein the halogen-containing gascomprises a fluorine-containing gas.
 20. The method of claim 17, whereinthe halogen-containing gas is NF3.
 21. The method of claim 13, whereinthe etching process comprises a wet etching process.
 22. The method ofclaim 21, wherein the etching process is performed by using hydrogenperoxide.
 23. The method of claim 13, wherein the conductive materialincludes tungsten, copper, or aluminum.